Field of the Invention
The present invention relates to a thin film transistor (TFT) array substrate and a liquid crystal display device including the same, and more particularly, to a fringe field switching (FFS) mode thin film transistor array substrate in which a pixel electrode and a common electrode are arranged on a planarizing insulating film so as to be opposed to each other through an insulating film, and a liquid crystal display device including the same.
Description of the Background Art
In general, a display mode of the liquid crystal display device is broadly classified into a twisted nematic (TN) mode, and a lateral electric field mode represented by in-plane switching (IPS) mode or a fringe field switching (FFS) mode. The liquid crystal display device of the lateral electric field mode is wide in viewing angle and high in contrast.
According to the liquid crystal display device of the IPS mode, display is implemented by applying a lateral electric field to liquid crystal sandwiched between opposed substrates, but since a pixel electrode and a common electrode to apply the lateral electric field are provided in the same layer, liquid crystal molecules positioned just above the pixel electrode cannot be sufficiently driven, so that its transmittance is low in this case.
Meanwhile, according to the FFS mode, since the common electrode and the pixel electrode are arranged through an interlayer insulating film, an oblique electric field (fringe electric field) is generated, so that the lateral electric field can be applied to liquid crystal molecules provided just above the pixel electrode, and can sufficiently drive them. Therefore, its viewing angle is wide, and its transmittance is higher than that of the IPS mode.
Recently, due to demands for further low power consumption and high aperture ratio, a structure of a FFS mode thin film transistor (TFT) array substrate including a thick planarizing insulating film has been proposed (Japanese Patent Application Laid-Open No. 2009-133954 and Japanese Patent Application Laid-Open No. 2007-226175, for example). When the thick planarizing insulating film is formed on a common wiring, a source wiring, and a TFT element, parasitic capacity of each signal line can be reduced, and power consumption can be low. In addition, since an upper surface of the TFT array substrate can be planarized by eliminating a difference in level among the wirings, a disorder in liquid crystal orientation conventionally generated in the level-difference part can be eliminated, and an area which does not contribute to the display is reduced, so that the aperture ratio is improved. Furthermore, since the pixel electrode is kept away from the signal line, the pixel electrode is not affected by the electric field generated from the signal line, so that it can be formed so as to overlap with the signal line. As a result, the pixel electrode can be enlarged.
According to a FFS mode liquid crystal device, liquid crystal is driven with a fringe electric field generated between a pixel electrode (or an opposed electrode) having slits provided in an upper layer, and the opposed electrode (or the pixel electrode) arranged under the pixel electrode through an insulating film. The pixel electrode and the opposed electrode are formed of a transparent conductive film composed of ITO or IZO, to prevent a pixel aperture ratio from becoming low. In addition, since holding capacitor is formed with the pixel electrode and the opposed electrode, it is not necessary to separately form holding capacitor in the pixel, unlike the TN mode liquid crystal device. In addition, as the interlayer insulating film provided between the pixel electrode and the opposed electrode becomes thin, electric field intensity becomes high, so that the liquid crystal can be driven at low voltage. For example, it is supposed that the thickness of the interlayer insulating film is preferably thinned to 200 nm to 400 nm.
However, regarding the above TFT array substrate including the thick planarizing insulating film, since a contact hole is deep, a new problem arises. As shown in FIG. 7 in the Japanese Patent Application Laid-Open Nos. 2009-133954 and 2007-226175, the pixel electrode and the common electrode need to be electrically connected to the drain electrode of the TFT and the common wiring through the contact holes. In a case where the planarizing insulating film is formed of a photosensitive resin or the like, an aspect ratio of the contact hole is high, so that the interlayer insulating film is not likely to be uniformly formed in the contact hole. In addition, as the interlayer insulating film becomes thin, a covering defect such as a pinhole is likely to be generated in a bottom and a slope part of the contact hole. When the pinhole is generated in the interlayer insulating film, an etching solution used when the upper transparent conductive film is processed passes through the pinhole and dissolves the lower transparent conductive film, which causes a connection defect and a resistance increase.
With respect to the above problem, Japanese Patent Application Laid-Open No. 2008-165134, for example, discloses a structure in which an inside of a contact hole is covered with a part of an upper layer electrode which is electrically isolated. However, this is not satisfactory in view of a problem in alignment accuracy in photoengraving process caused when a glass substrate is big, or a case where an etching residue is generated in an isolated part.
In addition, Japanese Patent Application Laid-Open No. 2009-036947, for example, discloses that an insulating film composed of a liquid material is formed in a contact hole to fill it. However, in order to completely fill the contact hole, a substantial amount of the liquid material needs to be applied to a substrate surface, and as a result, the insulating film is left between the pixel electrode and the opposed electrode, so that it is extremely difficult to reduce only the thickness of the insulating film between the pixel electrode and the opposed electrode. In addition, the liquid material is low in permittivity and a fringe electric field becomes weak, which is not preferable. Furthermore, the liquid material is high in cost.
In addition, the FFS structure including the planarizing insulating film has the problem that a large number of masks are needed in its producing process and production cost becomes high. For example, in a case where a TFT array substrate including a TFT element having a top gate structure is formed, nine photoengraving (photolithography) steps are needed in (1) patterning a light blocking electrode, (2) patterning a semiconductor layer, (3) patterning source/drain electrodes, (4) patterning a gate electrode, (5) forming a contact hole in a protective insulating film, (6) forming a contact hole in a planarizing insulating film, (7) patterning a lower layer electrode, (8) forming a contact hole in an interlayer insulating film, and (9) patterning an upper layer electrode. When the planarizing insulating film having the contact hole is used as a mask, (5) and (6) can be collectively performed, but still eight photoengraving steps are needed.